Because of its excellent electrical isolation properties and because of the ease of oxidizing silicon, a dielectric isolation tub of silicon dioxide is a commonly employed mechanism for isolating one integrated circuit island from another. Typically, a dielectrically isolated integrated circuit architecture will comprise a support substrate ("wafer handle") of thick deposited polycrystalline silicon atop which is disposed a silicon layer in which the active devices of the integrated circuit are formed. The respective devices are isolated from one another by tubs of dielectric material (e.g. silicon dioxide) which surround the devices and isolate the devices from adjacent silicon. Often the dielectric isolation tubs are formed by extending a silicon dioxide ring (formed by thermal oxidation or dielectrically refilled trench) down through the silicon to an underlying layer of silicon dioxide, so that each device is dielectrically isolated at the bottom thereof by the underlying silicon dioxide layer and on the sides thereof by the surrounding silicon dioxide ring.
One processing methodology for forming such a dielectric isolated integrated circuit structure, known by the acronym SIMOX, involves the separation of an upper, thin (1,000 .ANG.-3,000 .ANG.) portion of a monocrystalline silicon substrate, wherein devices are to be formed, from the lower portion of the substrate by implanting oxygen ions (typical implant dose 1.0.times.10 .sup.18 to 2.4.times.10.sup.18 O.sup.+ cm .sup.-2) into the substrate to form a buried (separated) dielectric layer (typical thickness 1,600 .ANG.-5,000 .ANG.). In the course of this Separation by IMplanted OXygen (SIMOX) process, the thin upper portion of the substrate in which circuit devices are to be formed accumulates damage by the passage of the oxygen ions therethrough to that buried portion of the substrate whereat the (dielectric) silicon dioxide layer is formed. As a result, the substrate must be annealed (usually at a temperature in a range of 1,150.degree. C. to 1,275.degree. C.) to heal damage in the thin silicon layer.
In a recently published article by Nakashima et al, entitled "High-Voltage CMOS SIMOX Technology and Its Application to a BSH-LSI", IEEE Transactions on Electron Devices, Vol. ED-33, No. 1, ppg. 126, Jan. 1986, it has been reported that, depending upon the conditions of the oxygen implantation step, the subsequent annealing step may cause the formation of an electric field shielding (EFS) layer of oxygen-doped polycrystalline silicon having a thickness on the order of several hundred angstroms between the buried silicon dioxide layer and the thin crystalline surface silicon layer. In particular, SIMOX substrates receiving an oxygen-implant dose in the above range (e.g. 1.8.times.10.sup.18 O.sup.+ cm .sup.-2) have been found to exhibit an EFS layer after the annealing at 1,150.degree. C. for two hours in a nitrogen atmosphere, when ion implantation beam current density is restricted to a range on the order of 12.5 to 17.5.mu.A cm.sup.-2 (when using an Extrion 200-20A implanter with standard wafer holders).
Contiguous with the top of the thin EFS polycrystalline layer is a thin (several hundred .ANG.) interfacial layer of silicon dioxide that isolates the surface monocrystalline silicon from the active polycrystalline EFS layer. Depending upon the anneal temperature, oxide precipitates may also be present above the polycrystalline EFS layer. Because of the presence of the EFS layer, when a back-surface voltage is applied to the substrate, the density of localized states in the polysilicon band gap effectively "shields", or terminates, the electric field lines arising from the substrate back-gate. Consequently, devices formed in the annealed crystalline silicon surface layer are vertically isolated from variations in substrate potential by the EFS layer, while the buried oxide layer continues to prevent leakage current between the top silicon layer and the underlying support substrate.
Now although the formation of such an EFS layer constitutes a marked improvement over conventional buried dielectric architectures, the conventional processing methodology employed to form such a layer suffers from a number of drawbacks that make it less practical from a manufacturing standpoint.
More particularly, the dose rate of the oxygen implant to create the requisite amorphous layer from which the oxygen doped polycrystalline silicon EFS layer will be formed during the subsequent annealing step is not compatible with a reasonably short implant time (on the order of several hours) using present day ion implantation equipment that lacks controllable, uniform active cooling. Therefore, high wafer throughput is not achieved. Indeed, the implantation of a high dose (of order 2.times.10.sup.18 O.sup.+ cm.sup.-2) of oxygen ions over a period of only several hours would require excessively high beam currents, i.e. a high dose rate, resulting in a wafer temperature in excess of 400.degree. C. (and typically in the neighborhood of 500.degree.-600.degree. C). Such a wafer temperature effectively imparts an in situ annealing of the substrate during oxygen implantation, which prevents the formation of an amorphous layer, which is a precursor to the EFS layer at the buried oxide interface. Consequently, the beam current must be reduced in order to keep the substrate temperature low, thereby necessitating a substantial increase in the time required to accomplish the implantation (a time period typically on the order of 8 to 16 hours). In other words, although the formation of an EFS layer contiguous with a buried oxide layer in a dielectrically isolated integrated circuit structure is electronically advantageous, when contrasted with nonshielded structures, the time required to manufacture such a structure using the processing methodology described in the above-referenced literature practically negates introduction of the architecture into the high-volume integrated circuit marketplace.